Process-Variation Resilient and Voltage-Scalable DCT Architecture for Robust Low-Power Computing

In this paper, we present a novel discrete cosine transform (DCT) architecture that allows aggressive voltage scaling for low-power dissipation, even under process parameter variations with minimal overhead as opposed to existing techniques. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors appear only from the long paths that are designed to be less contributive to output quality. The proposed architecture allows a graceful degradation in the peak SNR (PSNR) under aggressive voltage scaling as well as extreme process variations. Results show that even under large process variations (±3σ around mean threshold voltage) and aggressive supply voltage scaling (at 0.88 V, while the nominal voltage is 1.2 V for a 90-nm technology), there is a gradual degradation of image quality with considerable power savings (71% at PSNR of 23.4 dB) for the proposed architecture, when compared to existing implementations in a 90-nm process technology.

[1]  Kaushik Roy,et al.  Process Variation Tolerant Low Power DCT Architecture , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[2]  T. Fujita,et al.  A 0.9 V 150 MHz 10 mW 4 mm/sup 2/ 2-D discrete cosine transform core processor with variable-threshold-voltage scheme , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[3]  A. Chandrakasan,et al.  A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization , 1999, IEEE Journal of Solid-State Circuits.

[4]  Magdy Bayoumi,et al.  Energy aware distributed arithmetic DCT architectures , 2003, 2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682).

[5]  Konstantinos Konstantinides,et al.  Image and Video Compression Standards: Algorithms and Architectures , 1997 .

[6]  Naresh R. Shanbhag,et al.  Reliable low-power digital signal processing via reduced precision redundancy , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  B. M. Gordon,et al.  Supply and threshold voltage scaling for low power CMOS , 1997, IEEE J. Solid State Circuits.

[8]  Kaushik Roy,et al.  Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[9]  Kaushik Roy,et al.  Low-Power CMOS VLSI Circuit Design , 2000 .

[10]  Kaushik Roy,et al.  Statistical timing analysis using levelized covariance propagation , 2005, Design, Automation and Test in Europe.

[11]  David G. Messerschmitt,et al.  Digital video in a fading interference wireless environment , 1996, 1996 IEEE International Conference on Acoustics, Speech, and Signal Processing Conference Proceedings.

[12]  Douglas L. Jones,et al.  Efficient wireless image transmission under a total power constraint , 1998, 1998 IEEE Second Workshop on Multimedia Signal Processing (Cat. No.98EX175).

[13]  G.S. Moschytz,et al.  Practical fast 1-D DCT algorithms with 11 multiplications , 1989, International Conference on Acoustics, Speech, and Signal Processing,.

[14]  Douglas L. Jones,et al.  Total System Energy Minimization for Wireless Image Transmission , 2001, J. VLSI Signal Process..

[15]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[16]  Chaitali Chakrabarti,et al.  Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering , 2007, ICCAD 2007.

[17]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[18]  B. Cline,et al.  Analysis and modeling of CD variation for statistical static timing , 2006, ICCAD '06.

[19]  Jen-Shiun Chiang,et al.  A high throughput 2-dimensional DCT/IDCT architecture for real-time image and video system , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[20]  Kaushik Roy,et al.  Low power reconfigurable DCT design based on sharing multiplication , 2002, 2002 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[21]  Ahmed H. Tewfik,et al.  Adaptive low power multimedia wireless communications , 1997, Proceedings of First Signal Processing Society Workshop on Multimedia Signal Processing.

[22]  Doris Schmitt-Landsiedel,et al.  The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits , 1996, ISLPED '96.