NAND overview: from memory to systems

It was in 1965, just after the invention of the bipolar transistor by W. Shockley, W. Brattain and J. Bardeen, that Gordon Moore, co-founder of Intel, observed that the number of transistors per square centimeter in a microchip doubled every year. Moore thought that such trend would have proven true for the years to come as well, and indeed in the following years the density of active components in an integrated circuit kept on doubling every 18 months. For example, in the 18 months that elapsed between the Pentium processor 1.3 and the Pentium-4, the number of transistors grew from 28 to 55 million.

[1]  Y. Iwata,et al.  Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory , 2007, 2007 IEEE Symposium on VLSI Technology.

[2]  R. Fowler,et al.  Electron Emission in Intense Electric Fields , 1928 .

[3]  Chang-Gyu Hwang.  New Paradigms in the Silicon Industry , 2006, 2006 International Electron Devices Meeting.

[4]  Makoto Motoyoshi,et al.  Through-Silicon Via (TSV) , 2009, Proceedings of the IEEE.

[5]  Y. Iwata,et al.  Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices , 2006, 2009 Symposium on VLSI Technology.

[6]  G. Torelli,et al.  40-mm/sup 2/ 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory , 2000, IEEE Journal of Solid-State Circuits.

[7]  Sanjay S. Talreja,et al.  A 50nm 8Gb NAND Flash Memory with 100MB/s Program Throughput and 200MB/s DDR Interface , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[8]  Giovanni Campardo,et al.  Memory mass storage , 2011 .

[9]  Mitsumasa Koyanagi,et al.  High-Density Through Silicon Vias for 3-D LSIs , 2009, Proceedings of the IEEE.

[10]  Hiroshi Motoda,et al.  A Flash-Memory Based File System , 1995, USENIX.

[11]  Youngjoon Choi,et al.  A High Performance Controller for NAND Flash-based Solid State Disk (NSSD) , 2006, 2006 21st IEEE Non-Volatile Semiconductor Memory Workshop.

[12]  Kinam Kim,et al.  Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node , 2006, 2006 International Electron Devices Meeting.

[13]  Shinji Miyamoto,et al.  A 120mm2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[14]  Luca Crippa,et al.  A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[15]  Y. Takeuchi,et al.  A compact on-chip ECC for low cost flash memories , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[16]  Sang Lyul Min,et al.  A space-efficient flash translation layer for CompactFlash systems , 2002, IEEE Trans. Consumer Electron..

[17]  Roberto Ravasio,et al.  Error Correction Codes for Non-Volatile Memories , 2008 .

[18]  Soonwook Hwang,et al.  A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[19]  Rino Micheloni,et al.  VLSI-design of non-volatile memories , 2005 .