An 8 G connections-per-second 54 mW digital neural network chip low-power chain-reaction architecture

A high-speed digital neural-network chip which uses a polyhedric discrimination neuron (PDN) model and a low-power chain-reaction (LCR) architecture is presented. The chip contains 832 fully implemented digital synapse units with 8-b weights which form 13 neurons on a 10.3*14.1 mm/sup 2/ die using 0.8- mu m CMOS technology. A computational speed of 8 billion connections-per-second (GCPS) is achieved with 54-mW power dissipation. The forward propagation time of 104 ns is the fastest reported for a digital neural network chip. These features make possible large-scale neural network chips and systems.<<ETX>>