Most FPGAs use Look-Up Table (LUT) as the basic logic block. Input sharing look-up table (ISLUT) architecture is a cluster architecture, which can be configured as one 6-input LUT, two smaller LUTs or other modes. In this paper, several ISLUT architectures are added into Verilog-to-Routing (VTR) tool to compare with standard 6-input basic logic element (BLE6) architecture. Experimental results show that those input sharing architectures can achieve an 18.02% improvement for critical path delay and a 35.28% improvement for total used logic block area on average compared with standard BLE6. Among all those modes, the architecture that consists of one 5-input LUT, one 4-input LUT and two 3-input LUTs shows a better performance of 19.66% for the critical path delay and 37.68% for total used logic block area compared with standard BLE6. It also shows 14.28% improvement for the critical path delay and 10.00% for total used logic block area can be achieved compared with the ALM architecture.
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