Circuit delay computation based on ITTPN

Circuit delay computation is important in circuit systems. Petri net can reveal the structure information and dynamic behavior of systems. In this paper the circuit delay computation is concerned based on Petri net. T-Timed Petri net with special inhibitor arcs (ITTPN) is extended. A direct translation method from combinational circuit to ITTPN based on fixed delay model under the assumption of floating mode operation is introduced and a circuit delay computation algorithm based on complete finite prefix is proposed. Finally, an example is included to illustrate the method efficiency.

[1]  David Hung-Chang Du,et al.  Path sensitization in critical path problem [logic circuit design] , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Han-Pang Huang,et al.  Modeling and emulation of a furnace in IC fab based on colored-timed Petri net , 1998 .

[3]  Alexandre Yakovlev,et al.  Automated Verification of Asynchronous Circuits Using Circuit Petri Nets , 2008, 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems.

[4]  Shih-Chieh Chang,et al.  Efficient Boolean Characteristic Function for Timed Automatic Test Pattern Generation , 2009, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  David Hung-Chang Du,et al.  Path sensitization in critical path problem , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[6]  Walter Vogler,et al.  An Improvement of McMillan's Unfolding Algorithm , 2002, Formal Methods Syst. Des..

[7]  N. Ranganathan,et al.  Petri net modeling of gate and interconnect delays for power estimation , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[8]  Robert K. Brayton,et al.  A Timed Automaton-Based Method for Accurate Computation of Circuit Delay in the Presence of Cross-Talk , 1998 .

[9]  Ping Xu,et al.  Sneak timing analysis based on time Petri net in power system , 2009, 2009 4th IEEE Conference on Industrial Electronics and Applications.

[10]  Hossein Pedram,et al.  Performance Evaluation of Asynchronous Circuits with Choice Using Abstract Probabilistic Timed Petri Nets , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

[11]  Joao Marques-Silva,et al.  Satisfiability models and algorithms for circuit delay computation , 2002, TODE.

[12]  Walter Vogler,et al.  An Improvement of McMillan's Unfolding Algorithm , 1996, Formal Methods Syst. Des..

[13]  Pallab Dasgupta,et al.  Event propagation for accurate circuit delay calculation using SAT , 2008, TODE.