On concurrent error location and correction of FFT networks

Fault tolerance has been one of the major issues for the VLSI based FFT networks. In this paper, two efficient approaches for concurrent error location and correction of FFT networks are proposed. Using our approach, a faulty component can be located at an additional try followed by log/sub 2/m comparisons of m corrupted outputs. An error can also be corrected, once it is detected, at a small modification of basic module with an additional try. Moreover, our approaches are general in the sense that they can be implemented with any concurrent error detection scheme employing a checksum approach for FFT networks. >

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