Software Transactional Memory Friendly Slot Schedulers

In this paper, we discuss the design space of highly concurrent linearizable data structures for slot scheduling. We observe that it is not possible to have high fairness across threads, and maximize throughput of the entire system simultaneously. Lock free algorithms are very fast, yet very unfair, and wait free algorithms follow the reverse trend. We thus propose a class of algorithms using software transactional memory STM that are in the middle of the spectrum. They equitably balance fairness and throughput, and are much simpler to design and verify.

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