Transient fault characterization in dynamic noisy environments

Technology trends are increasing the frequency of serious transient (soft) faults in digital systems. For example, ICs are becoming more susceptible to cosmic radiation, and are being embedded in applications with dynamic noisy environments. We propose a generic framework for representing such faults and characterizing them on-line. We formally define the impact of a transient fault in terms of three basic parameters: frequency, observability and severity. We distinguish fault modes in systems whose noise environment changes dynamically. Based on these ideas, the problem of designing on-line architectures for transient fault characterization is formulated and analyzed for several optimization goals. Finally, experiments are described that determine transient fault impact and the corresponding tests for various simulated fault modes of the ISCAS-89 benchmark circuits

[1]  Edward J. McCluskey,et al.  An experimental chip to evaluate test techniques experiment results , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[2]  Abhijit Chatterjee,et al.  Sizing CMOS circuits for increased transient error tolerance , 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

[3]  N. Kawamoto,et al.  Comparison between neutron-induced system-SER and accelerated-SER in SRAMS , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[4]  Michel Pignol,et al.  How to cope with SEU/SET at system level? , 2005, 11th IEEE International On-Line Testing Symposium.

[5]  R. Baumann,et al.  Neutron-induced boron fission as a major source of soft errors in deep submicron SRAM devices , 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).

[6]  Nur A. Touba,et al.  Cost-effective approach for reducing soft error failure rate in logic circuits , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[7]  Thierry Paul,et al.  Quantum computation and quantum information , 2007, Mathematical Structures in Computer Science.

[8]  Håkan Sivencrona,et al.  Byzantine Fault Tolerance, from Theory to Reality , 2003, SAFECOMP.

[9]  M.J. Gadlage,et al.  Modeling and verification of single event transients in deep submicron technologies , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[10]  Robert S. Swarz,et al.  Reliable Computer Systems: Design and Evaluation , 1992 .

[11]  M. Baze,et al.  Attenuation of single event induced pulses in CMOS combinational logic , 1997 .

[12]  D. C. Wilkinson,et al.  Spacecraft problems in association with episodes of intense solar activity and related terrestrial phenomena during March 1991 , 1992 .

[13]  Chenming Hu,et al.  A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[14]  Sanjay J. Patel,et al.  Characterizing the effects of transient faults on a high-performance processor pipeline , 2004, International Conference on Dependable Systems and Networks, 2004.

[15]  T. May,et al.  Alpha-particle-induced soft errors in dynamic memories , 1979, IEEE Transactions on Electron Devices.

[16]  Y. Yagil,et al.  A systematic approach to SER estimation and solutions , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[17]  Susmita Sur-Kolay,et al.  A modeling approach for addressing power supply switching noise related failures of integrated circuits , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[18]  Sandeep K. Gupta,et al.  An ATPG for threshold testing: obtaining acceptable yield in future processes , 2002, Proceedings. International Test Conference.

[19]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[20]  E. Normand Single-event effects in avionics , 1996 .

[21]  Lloyd W. Massengill,et al.  Impact of scaling on soft-error rates in commercial microprocessors , 2002 .

[22]  P. P. Gelsinger Gigascale integration for teraops performance-challenges, opportunities, and new frontiers , 2004, DAC 2004.

[23]  E. Normand Single event upset at ground level , 1996 .

[24]  Toshihiro Sugii,et al.  Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages , 1999, IEEE J. Solid State Circuits.

[25]  Lloyd W. Massengill,et al.  Basic mechanisms and modeling of single-event upset in digital microelectronics , 2003 .

[26]  E. Nonnand Single Event Upsets in Implantable Cardioverter Defibrillators , 1998 .

[27]  F. W. Sexton,et al.  Critical charge concepts for CMOS SRAMs , 1995 .

[28]  Michael Nicolaidis,et al.  Embedded robustness IPs , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[29]  T. Matsuoka,et al.  Novel bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced isolation (SITOS) and gate to shallow-well contact (SSS-C) processes for ultra low power dual gate CMOS , 1996, International Electron Devices Meeting. Technical Digest.