Qualitative Analysis of CMOS Logic Full Adder and GDI Logic Full Adder using 18 nm FinFET Technology

In this paper we qualitatively analysed basic full adder circuitry, which is implemented using CMOS technology (28T) and GDI technique (10T) using 18nm FinFET technology. The primary objective is to optimize our conventional adder so that an experimental analysis is conducted in order to analyse these two distinct circuits with same operation in terms of Area, Propagation Delay, Power and Power-Delay-Product (PDP). All experimental analysis is carried using Cadence Virtuoso (cds-ff-mpt library is used for FinFET).