Fully Symbolic Model Checking of Timed Systems using Difference Decision Diagrams
暂无分享,去创建一个
Henrik Reif Andersen | Henrik Hulgaard | Jesper B. Møller | Jakob Lichtenberg | H. Andersen | Jesper B. Møller | H. Hulgaard | J. Lichtenberg
[1] Henrik Reif Andersen,et al. Difference Decision Diagrams , 1999, CSL.
[2] Felice Balarin,et al. Approximate reachability analysis of timed automata , 1996, 17th IEEE Real-Time Systems Symposium.
[3] Chris J. Myers,et al. Efficient timing analysis algorithms for timed state space exploration , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.
[4] AbadiMartín,et al. An old-fashioned recipe for real time , 1994 .
[5] Sergio Yovine,et al. KRONOS: a verification tool for real-time systems , 1997, International Journal on Software Tools for Technology Transfer.
[6] Robin Milner,et al. Communication and concurrency , 1989, PHI Series in computer science.
[7] R. K. Shyamasundar,et al. Introduction to algorithms , 1996 .
[8] Stavros Tripakis,et al. The Tool KRONOS , 1996, Hybrid Systems.
[9] J. Burch. Trace algebra for automatic verification of real-time concurrent systems , 1992 .
[10] Rajeev Alur,et al. The Theory of Timed Automata , 1991, REX Workshop.
[11] Edmund M. Clarke,et al. Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic , 1981, Logic of Programs.
[12] A. Pnueli,et al. Data-Structures for the Verification of Timed Automata , 1997, HART.
[13] Alan J. Hu,et al. Efficient Verification with BDDs using Implicitly Conjoined Invariants , 1993, CAV.
[14] Martín Abadi,et al. An old-fashioned recipe for real time , 1994, TOPL.
[15] Conrado Daws,et al. Verifying ET-LOTOS programmes with KRONOS , 1994, FORTE.
[16] Wang Yi,et al. Efficient Timed Reachability Analysis Using Clock Difference Diagrams , 1998, CAV.
[17] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[18] Edmund M. Clarke,et al. Symbolic Model Checking: 10^20 States and Beyond , 1990, Inf. Comput..
[19] David L. Dill,et al. Approximations for verifying timing properties , 1994 .
[20] David L. Dill,et al. Timing Assumptions and Verification of Finite-State Concurrent Systems , 1989, Automatic Verification Methods for Finite State Systems.
[21] Tomas Rokicki. Representing and modeling digital circuits , 1994 .
[22] Conrado Daws,et al. Two examples of verification of multirate timed automata with Kronos , 1995, Proceedings 16th IEEE Real-Time Systems Symposium.
[23] Chris J. Myers,et al. Verification of Timed Systems Using POSETs , 1998, CAV.
[24] Henrik Reif Andersen,et al. On the Symbolic Verification of Timed Systems , 1999, CAV 1999.
[25] Bill Lin,et al. Efficient partial enumeration for timing analysis of asynchronous systems , 1996, DAC '96.
[26] Chris J. Myers,et al. Automatic Verification of Timed Circuits , 1994, CAV.
[27] Wang Yi,et al. UPPAAL in 1995 , 1996, TACAS.
[28] Wang Yi,et al. Uppaal in a nutshell , 1997, International Journal on Software Tools for Technology Transfer.
[29] M. Diaz,et al. Modeling and Verification of Time Dependent Systems Using Time Petri Nets , 1991, IEEE Trans. Software Eng..
[30] Thomas A. Henzinger,et al. Symbolic Model Checking for Real-Time Systems , 1994, Inf. Comput..
[31] Sérgio Vale Aguiar Campos,et al. Computing quantitative characteristics of finite-state real-time systems , 1994, 1994 Proceedings Real-Time Systems Symposium.
[32] Sergio Yovine,et al. Model Checking Timed Automata , 1996, European Educational Forum: School on Embedded Systems.
[33] Amir Pnueli,et al. Data-Structures for the Verification of Timed Automata , 1997, HART.
[34] Amir Pnueli,et al. Some Progress in the Symbolic Verification of Timed Automata , 1997, CAV.