Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction Tunnel-FETs

Abstract This paper reports on the integration of vertical nTunnel FETs (TFETs) with SiGe hetero-junction and analyzes the presence of trap-assisted tunneling impacting the device behavior. Temperature measurements are used to distinguish the band-to-band tunneling (BTBT) from the trap-assisted tunneling (TAT). It is shown that TAT degrades the onset characteristic and the subthreshold swing of the devices. TCAD simulations are in good agreement with experimental data for a germanium content up to 44%, when including non-local TAT model and properly tuning the model’s parameters. Simulations also suggest that boosting the BTBT component, for example by further bandgap decrease (Ge source), or by other means should be beneficial in lowering the impact of trap-assisted tunneling, provided that the material defectivity does not worsen.

[1]  K. Saraswat,et al.  Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and ≪60mV/dec subthreshold slope , 2008, 2008 IEEE International Electron Devices Meeting.

[2]  Rita Rooyackers,et al.  Drain voltage dependent analytical model of tunnel field-effect transistors , 2011 .

[3]  N. Singh,et al.  Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires , 2009, IEEE Electron Device Letters.

[4]  H. Riel,et al.  One-Dimensional Nanoelectronic Devices - Towards the Quantum Capacitance Limit , 2008, 2008 Device Research Conference.

[5]  Joachim Knoch,et al.  Impact of electrostatics and doping concentration on the performance of silicon tunnel field-effect transistors , 2009 .

[6]  S. Sedlmaier,et al.  Vertical tunnel field-effect transistor , 2004, IEEE Transactions on Electron Devices.

[7]  Yee-Chia Yeo,et al.  Silicon-based tunneling field-effect transistor with elevated germanium source formed on (110) silicon substrate , 2011 .

[8]  J. Sturm,et al.  Bandgap dependence of band-to-band tunneling and defect-mediated excess currents in SiGe/Si heterojunction tunnel diodes grown by RTCVD , 2009, 2009 Device Research Conference.

[9]  R. People,et al.  Calculation of critical layer thickness versus lattice mismatch for GexSi1−x/Si strained‐layer heterostructures , 1985 .

[10]  K. Kao,et al.  Direct and Indirect Band-to-Band Tunneling in Germanium-Based TFETs , 2012, IEEE Transactions on Electron Devices.

[11]  Rita Rooyackers,et al.  Impact of process and geometrical parameters on the electrical characteristics of vertical nanowire silicon n-TFETs , 2012 .

[12]  G. Groeseneken,et al.  Analytical model for point and line tunneling in a tunnel field-effect transistor , 2008, 2008 International Conference on Simulation of Semiconductor Processes and Devices.

[13]  A. R. Moore,et al.  Intrinsic Optical Absorption in Germanium-Silicon Alloys , 1958 .

[14]  F. Andrieu,et al.  Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible Tunnel FET performance , 2008, 2008 IEEE International Electron Devices Meeting.

[15]  A. Schenk.  A model for the field and temperature dependence of Shockley-Read-Hall lifetimes in silicon , 1992 .

[16]  T. Mayer,et al.  Experimental demonstration of 100nm channel length In0.53Ga0.47As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[17]  Rita Rooyackers,et al.  Silicide Engineering to Boost Si Tunnel Transistor Drive Current , 2011 .

[18]  R. Rooyackers,et al.  Performance Enhancement in Multi Gate Tunneling Field Effect Transistors by Scaling the Fin-Width , 2010 .

[19]  Zhixian Chen,et al.  Vertical Si-Nanowire $n$-Type Tunneling FETs With Low Subthreshold Swing ($\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature , 2011, IEEE Electron Device Letters.

[20]  K. Maex,et al.  Tunnel field-effect transistor without gate-drain overlap , 2007 .

[21]  K. Maex,et al.  Boosting the on-current of a n-channel nanowire tunnel field-effect transistor by source material optimization , 2008 .

[22]  Geert Hellings,et al.  Electrical TCAD Simulations of a Germanium pMOSFET Technology , 2010, IEEE Transactions on Electron Devices.

[23]  B. Sorée,et al.  Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor , 2010 .

[24]  G. Dewey,et al.  Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing , 2011, 2011 International Electron Devices Meeting.

[25]  R. Rooyackers,et al.  Drive current enhancement in p-tunnel FETs by optimization of the process conditions , 2011 .

[26]  Kaustav Banerjee,et al.  Vertical Si-Nanowire n-Type Tunneling FETs With Low Subthreshold Swing (≤ 50 mV/decade) at Room Temperature , 2011 .

[27]  J. Appenzeller,et al.  Comparing carbon nanotube transistors - the ideal choice: a novel tunneling device design , 2005, IEEE Transactions on Electron Devices.

[28]  G. Amaratunga,et al.  Silicon surface tunnel transistor , 1995 .

[29]  E. Simoen,et al.  Impact of Donor Concentration, Electric Field, and Temperature Effects on the Leakage Current in Germanium p $+/$n Junctions , 2008, IEEE Transactions on Electron Devices.

[30]  C. Hu,et al.  Si tunnel transistors with a novel silicided source and 46mV/dec swing , 2010, 2010 Symposium on VLSI Technology.

[31]  K. Boucart,et al.  Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric , 2007, IEEE Transactions on Electron Devices.

[32]  R. Rooyackers,et al.  Observation of diameter dependent carrier distribution in nanowire-based transistors , 2011, Nanotechnology.

[33]  I. Eisele,et al.  Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering , 2005, IEEE Transactions on Electron Devices.

[34]  N. Cowern,et al.  Diffusion of boron in germanium at 800–900°C , 2004 .

[35]  C. Hu,et al.  Germanium-source tunnel field effect transistors with record high ION/IOFF , 2006, 2009 Symposium on VLSI Technology.