A 1Mb ROM with on chip ECC for yield enhancement

A 1Mb PROGRAMMABLE ROM, with on-chip ECC (ErrorCorrecting Code) circuits for yield enhancement and an on-chip substrate bias generator for high speed, fabricated by polycide gate Zg N-well CMOS technology, will be described. Organized as 128Kx8b, the ROM occupies an area of 78.8mm2. and is assembled in a 600-mil wide 28 pin DIP, as shown in Figure 1. A photomicrograph of the chip is shown in Figure 2. The memory cell array has an open-bit-line structure and is divided into four blocks, with horizontal metal bit lines and vertical polycide word lines. A block diagram of the ROM is shown in Figure 3. The sense amplifiers, main amplifiers, and 38 data bus lines are located between the pairs of bit lines. The single-row decoder/driver band is centered. The cell size is 6 x 6$, achieved by 2 p design rule. Dynamic circuits are employed to achieve fast access time and save active power dissipation, and internal clocks are generated by address transition detector circuits. All bit lines are precharged by the first clock ($a ) as shown in Figure 4. The data signals from the cells selected by the word line and the select signal (Q2 ) are amplified by the CMOS dynamic sense amplifiers and latched by the main amplifiers. Therefore, 38b signals, consisting of 32 data bits and 6 check bits for ECC, are simultaneously read out from the separated cells and entered into the ECC circuits. As shown in Figure 3, the corrected 32 data bits are transfered to a nibble decoder and divided into four blocks. The output buffers drive 8 bits. The ECC circuits consume less than 20% of the total chip area. Even though they increase chip area, the theoretical yield can be enhanced about three times. This has been confirmed by measurement also. As the number of data bits read out in the same cycle increases, the area for the ECC circuits also increases, while the ratio of the check bits decreases. To minimize chip area, 32 data bits were introduced. The access time increased by ECC circuits is less than 15%. These ECC circuits can correct an error bit contained in the 32 data bits, and even adjacent error bits by reading out the separated memory cells. The maximum number of errors that can be corrected by this on-chip ECC is 32K errors/chip. Figure 5 shows the Fail Bit Map (FBM) before and after correction by the ECC circuits. The horizontal lines in Figure 5 ( a ) indicate the presence of error bits. In Figure 5 ( b ) these lines are deleted from the FBM by the ECC circuits. To realize high speed by the reduction of the diffusion capacitance in the bit lines, N-well CMOS devices with an onchip substrate bias generator are employed. Typical address access time is 150ns and nibble access time is 30ns, as shown in Figure 6. Using the nibble cycle increases the data transfer rate. The time to read out 32b is 600ns with four normal cycles, but is only 240ns with one normal and three nibble cycles. Active power is 70mW at a 25011s cycle time and standby power is 2mW. Table I summarizes typical characteristics of the ROM.