An efficient transparent test scheme for embedded word-oriented memories

Memory cores are usually the densest portion with the smallest feature size in system-on-chip (SOC) designs. The reliability of memory cores thus has a heavy impact on the reliability of SOCs. The transparent test is a useful technique for improving the reliability of memories during their life time. The paper presents a systematic algorithm used for transforming a bit-oriented march test into a transparent word-oriented march test. The transformed transparent march test has shorter test complexity compared with those proposed previously (Nicolaidis, M., IEEE Trans. Computers, vol.45, no.10, p.1141-56, 1996; Thaller, K. and Steininger, A., IEEE Trans. Reliability, vol.52, no.4, p.413-22, 2003). For example, if a memory with 32-bit words is tested with March C-, the time complexity of the transparent word-oriented test transformed by the proposed scheme is only about 56% and 19% of the time complexity of the transparent word-oriented test converted by the schemes reported by Nicolaidis and by Thaller and Steininger, respectively.

[1]  Michael Nicolaidis,et al.  Theory of Transparent BIST for RAMs , 1996, IEEE Trans. Computers.

[2]  Mark G. Karpovsky,et al.  Transparent memory testing for pattern sensitive faults , 1994, Proceedings., International Test Conference.

[3]  Andreas Steininger,et al.  A transparent online memory test for simultaneous detection of functional faults and soft errors in memories , 2003, IEEE Trans. Reliab..

[4]  Sungho Kang,et al.  DPSC SRAM transparent test algorithm , 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

[5]  Ad J. van de Goor,et al.  Using March Tests to Test SRAMs , 1993, IEEE Des. Test Comput..

[6]  Jin-Fu Li,et al.  Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test , 2002, J. Electron. Test..

[7]  Bruce F. Cockburn,et al.  A transparent built-in self-test scheme for detecting single V-coupling faults in RAMs , 1994, Proceedings of IEEE International Workshop on Memory Technology, Design, and Test.

[8]  Cheng-Wen Wu,et al.  A Programmable BIST Core for Embedded DRAM , 1999, IEEE Des. Test Comput..

[9]  V. N. Yarmolik,et al.  Automatic generation of symmetric transparent March memory tests , 2003, The Experience of Designing and Application of CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th International Conference..

[10]  Frans P. M. Beenker,et al.  A realistic fault model and test algorithms for static random access memories , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Ad J. van de Goor,et al.  Simulation and development of short transparent tests for RAM , 2001, Proceedings 10th Asian Test Symposium.

[12]  Georgi Gaydadjiev,et al.  March U: a test for unlinked memory faults , 1997 .

[13]  Michael Nicolaidis,et al.  TRANSPARENT BIST FOR RAMS , 1992, Proceedings International Test Conference 1992.

[14]  Paolo Prinetto,et al.  Industrial BIST of embedded RAMs , 1995, IEEE Design & Test of Computers.

[15]  Mark G. Karpovsky,et al.  Transparent memory BIST , 1994, Proceedings of IEEE International Workshop on Memory Technology, Design, and Test.

[16]  Frans P. M. Beenker,et al.  Fault modeling and test algorithm development for static random access memories , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[17]  Jin-Fu Li,et al.  A built-in self-test and self-diagnosis scheme for embedded SRAM , 2000, Proceedings of the Ninth Asian Test Symposium.

[18]  Bruce F. Cockburn.  Deterministic tests for detecting singleV-coupling faults in RAMs , 1994, J. Electron. Test..

[19]  Jin-Fu Li,et al.  A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM , 2002, J. Electron. Test..

[20]  Hans-Joachim Wunderlich,et al.  Symmetric transparent BIST for RAMs , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).