On the implementation of shifters, multipliers, and dividers in VLSI floating point units

Several options for the implementation of combinatorial shifters, multipliers, and dividers for a VLSI floating point unit are presented and compared. The comparisons are made in the context of a single chip implementation in light of the constraints imposed by currently available MOS technology.

[1]  Vojin G. Oklobdzija,et al.  Some optimal schemes for ALU implementation in VLSI technology , 1985, 1985 IEEE 7th Symposium on Computer Arithmetic (ARITH).

[2]  O. L. Macsorley High-Speed Arithmetic in Binary Computers , 1961, Proceedings of the IRE.

[3]  Damiel E. Atkins Higher-Radix Division Using Estimates of the Divisor and Partial Remainders , 1968, IEEE Transactions on Computers.

[4]  F. Ishino,et al.  A single chip 80b floating point processor , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.