论文信息 - 9 bit 3.3 M samples/s pipelined A-to-D converter using a new mismatch insensitive algorithm

9 bit 3.3 M samples/s pipelined A-to-D converter using a new mismatch insensitive algorithm

This paper presents the implementation and testing results for a pipelined analog-to-digital converter, using a new mismatch insensitive algorithm. The testing results show that the ADC resolves 9 bits at 3.3 M samples/s without any digital error correction.

Yalin Ren | Bosco Leung | Yuh-Min Lin

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