3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans

We propose new 3D 2-layer and 3-layer NoC architectures that utilize homogeneous regular mesh networks on a separate layer and one or two heterogeneous floorplanning layers. These architectures combine the benefits of compact heterogeneous floorplans and of regular mesh networks. To demonstrate these benefits, a design methodology that integrates floorplanning, routers assignment, and cycle-accurate NoC simulation is proposed. The implementation of the NoC on a separate layer offers an additional area that may be utilized to improve the network performance by increasing the number of virtual channels, buffers size, or mesh size. Experimental results show that increasing the number of virtual channels rather than the buffers size has a higher impact on network performance. Increasing the mesh size can significantly improve the network performance under the assumption that the clock frequency is given by the length of the physical links. In addition, the 3-layer architecture can offer significantly better network performance compared to the 2-layer architecture.

[1]  S. Borkar,et al.  An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[2]  Krishnan Srinivasan,et al.  A Low Complexity Heuristic for Design of Custom Network-on-Chip Architectures , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[3]  David Wentzlaff,et al.  Processor: A 64-Core SoC with Mesh Interconnect , 2010 .

[4]  Krishnan Srinivasan,et al.  Linear programming based techniques for synthesis of network-on-chip architectures , 2006, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[5]  Chita R. Das,et al.  A novel dimensionally-decomposed router for on-chip communication in 3D architectures , 2007, ISCA '07.

[6]  Tapani Ahonen,et al.  Topology optimization for application-specific networks-on-chip , 2004, SLIP '04.

[7]  Axel Jantsch,et al.  Network on Chip : An architecture for billion transistor era , 2000 .

[8]  Bill Lin,et al.  A Layer-Multiplexed 3D On-Chip Network Architecture , 2009, IEEE Embedded Systems Letters.

[9]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[10]  Axel Jantsch,et al.  Scalability of network-on-chip communication architecture for 3-D meshes , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[11]  S. K. Kim,et al.  Three-dimensional integration: technology, use, and issues for mixed-signal applications , 2003 .

[12]  Luca P. Carloni,et al.  Networks-on-chip in emerging interconnect paradigms: Advantages and challenges , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[13]  Bryan Black,et al.  Design and Fabrication of 3D Microprocessors , 2006 .

[14]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[15]  Chita R. Das,et al.  MIRA: A Multi-layered On-Chip Interconnect Router Architecture , 2008, 2008 International Symposium on Computer Architecture.

[16]  Norbert Wehn,et al.  Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip , 2006, 9th EUROMICRO Conference on Digital System Design (DSD'06).

[17]  Pascal Benoit,et al.  A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips , 2009, Int. J. Reconfigurable Comput..

[18]  Jian Xu,et al.  Demystifying 3D ICs: the pros and cons of going vertical , 2005, IEEE Design & Test of Computers.

[19]  Shashi Shekhar,et al.  Multilevel hypergraph partitioning: applications in VLSI domain , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[20]  Krishnan Srinivasan,et al.  Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  William J. Dally,et al.  A delay model and speculative architecture for pipelined routers , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[22]  Edmund J. Sprogis,et al.  Wafer-level 3D integration technology , 2008, IBM J. Res. Dev..

[23]  Natalie D. Enright Jerger,et al.  Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[24]  Bill Lin,et al.  Design of application-specific 3D Networks-on-Chip architectures , 2008, 2008 IEEE International Conference on Computer Design.

[25]  L. Benini,et al.  Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[26]  Luca Benini,et al.  A low-overhead fault tolerance scheme for TSV-based 3D network on chip links , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[27]  Kees G. W. Goossens,et al.  A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic , 2007, VLSI Design.

[28]  Mahmut T. Kandemir,et al.  Design and Management of 3D Chip Multiprocessors Using Network-in-Memory , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

[29]  Li Shang,et al.  Dynamic voltage scaling with links for power optimization of interconnection networks , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

[30]  Jun Yang,et al.  A low-radix and low-diameter 3D interconnection network design , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[31]  Luca Benini,et al.  Synthesis of networks on chips for 3D systems on chips , 2009, 2009 Asia and South Pacific Design Automation Conference.

[32]  An-Yeu Wu,et al.  Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks , 2008, IEEE Transactions on Computers.

[33]  Jörg Henkel,et al.  A design methodology for application-specific networks-on-chip , 2006, TECS.

[34]  Narayanan Vijaykrishnan,et al.  Thermal-aware IP virtualization and placement for networks-on-chip architecture , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[35]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[36]  Wenhua Dou,et al.  From 2D to 3D NoCs: A case study on worst-case communication performance , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[37]  Yao-Wen Chang,et al.  B*-Trees: a new representation for non-slicing floorplans , 2000, DAC.

[38]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[39]  J. Munkres.  ALGORITHMS FOR THE ASSIGNMENT AND TRANSIORTATION tROBLEMS* , 1957 .

[40]  Tobias Bjerregaard,et al.  A survey of research and practices of Network-on-chip , 2006, CSUR.

[41]  L. Benini,et al.  Designing Application-Specific Networks on Chips with Floorplan Information , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[42]  Cristinel Ababei,et al.  A Framework for 2.5D NoC Exploration Using Homogeneous Networks over Heterogeneous Floorplans , 2009, 2009 International Conference on Reconfigurable Computing and FPGAs.

[43]  Manfred Glesner,et al.  Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management , 2009, VLSI Design.

[44]  Eby G. Friedman,et al.  3-D Topologies for Networks-on-Chip , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[45]  Srinivasan Murali,et al.  SUNMAP: a tool for automatic topology selection and generation for NoCs , 2004, Proceedings. 41st Design Automation Conference, 2004..

[46]  Radu Marculescu,et al.  Energy- and performance-aware mapping for regular NoC architectures , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[47]  Partha Pratim Pande,et al.  Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation , 2009, IEEE Transactions on Computers.