Full-wave PEEC time-domain method for the modeling of on-chipinterconnects

With the advances in the speed of high-performance chips, inductance effects in some on-chip interconnects have become significant. Specific networks such as clock distributions and other highly optimized circuits are especially impacted by inductance. Several difficult aspects have to be overcome to obtain valid waveforms for problems where inductances contribute significantly. Mainly, the geometries are very complex and the interactions between the capacitive and inductive currents have to be taken into account simultaneously. In this paper, we show that a full-wave partial element equivalent circuit method, which includes the delays among the partial elements, leads to an efficient solver enabling the analysis of large meaningful problems. Applying this method to several examples leads to helpful insights for realistic very large scale integration wiring problems. It is shown in this paper that the impact overshoot, reflections, and inductive coupling are critical for the design of critical on-chip interconnects.

[1]  S. Wong,et al.  On-chip inductance modeling of VLSI interconnects , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[2]  Andreas C. Cangellaris,et al.  Passivity validation for numerically-generated electromagnetic macromodels , 1999, 1999 IEEE International Symposium on Electromagnetic Compatability. Symposium Record (Cat. No.99CH36261).

[3]  Giulio Antonini,et al.  PEEC modeling of lightning protection systems and coupling to coaxial cables , 1998 .

[4]  R. Saleh.  FastCap : A Multipole Accelerated 3-D Capacitance Extraction Program , 1991 .

[5]  Keith A. Jenkins,et al.  When are transmission-line effects important for on-chip interconnections? , 1997 .

[6]  Alina Deutsch,et al.  Designing the best clock distribution network , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[7]  P. Roper,et al.  Full copper wiring in a sub-0.25 /spl mu/m CMOS ULSI technology , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[8]  Ronald A. Rohrer,et al.  Three dimensional circuit oriented electromagnetic modeling for VLSI interconnects , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[9]  Raminderpal Singh.  Harmony: Static Noise Analysis of Deep Submicron Digital Integrated Circuits , 2002 .

[10]  R. J. Joseph,et al.  Advances in Computational Electrodynamics: The Finite - Di erence Time - Domain Method , 1998 .

[11]  J. Kong,et al.  A hybrid method for the calculation of the resistance and inductance of transmission lines with arbitrary cross sections , 1991 .

[12]  Andreas C. Cangellaris,et al.  Hybrid electromagnetic modeling of noise interactions in packaged electronics based on the partial-element equivalent-circuit formulation , 1997 .

[13]  K. Kim,et al.  Wireless interconnection in a CMOS IC with integrated antennas , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[14]  Albert E. Ruehli,et al.  Inductance calculations in a complex integrated circuit environment , 1972 .

[15]  M. Mizuno,et al.  On-chip multi-GHz clocking with transmission lines , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[16]  M. Soyuer,et al.  A fully-monolithic SiGe differential voltage-controlled oscillator for 5 GHz wireless applications , 2000, 2000 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers (Cat. No.00CH37096).

[17]  Albert E. Ruehli,et al.  Comparison of differential and common mode response for short transmission line using PEEC models , 1996 .

[18]  A. E. Ruehii.  Inductance Calculations in a Complex Integrated Circuit Environment , 2002 .

[19]  S. Ahmed,et al.  FACET - A CAE System for RF Analogue Simulation Including Layout , 1989, 26th ACM/IEEE Design Automation Conference.

[20]  Yehea I. Ismail,et al.  Equivalent Elmore delay for RLC trees , 1999, DAC '99.

[21]  Keith A. Jenkins,et al.  Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocessor , 1998, IEEE J. Solid State Circuits.

[22]  Mattan Kamon,et al.  A mixed nodal-mesh formulation for efficient extraction and passive reduced-order modeling of 3D interconnects , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[23]  J.N. Burghartz,et al.  Novel substrate contact structure for high-Q silicon-integrated spiral inductors , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[24]  Jacob K. White,et al.  Layout techniques for minimizing on-chip interconnect self-inductance , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[25]  H. Hasegawa,et al.  Properties of Microstrip Line on Si-SiO/sub 2/ System , 1971 .

[26]  A. Ruehli.  Equivalent Circuit Models for Three-Dimensional Multiconductor Systems , 1974 .

[27]  Zheng-Yu Yuan,et al.  Computer-aided analysis of on-chip interconnects near semiconductorsubstrate for high-speed VLSI , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[28]  Jacob K. White,et al.  Recent improvements for fast inductance extraction and simulation [packaging] , 1998, IEEE 7th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.98TH8370).

[29]  Ali M. Niknejad,et al.  Analysis, design, and optimization of spiral inductors and transformers for Si RF ICs , 1998, IEEE J. Solid State Circuits.