Efficient parasitic substrate modeling for monolithic mixed-A/D circuit design and verification

Parasitic analog-digital noise coupling has been identified as a key issue facing designers of mixed-signal integrated circuits. In particular, signal crosstalk through the common chip substrate has become increasingly problematic. This paper demonstrates a methodology for developing simulation, synthesis, and verification models to analyze the global electrical behavior of the non-ideal semiconductor substrate. First, a triangular discretization method is employed to generate RC equivalent-circuit substrate models which are far less complex than those formulated by conventional techniques. The networks are then accurately approximated for subsequent analysis by an efficient reduction algorithm which uses a well-conditioned Lanczos moment-matching process. Through congruence transformations, the network admittance matrices are transformed to reduced equivalents which are easily post-processed to derive passive, SPICE-compatible netlist representations of the reduced models. The pure-RC properties of the extracted substrate networks are fully exploited to formulate an efficient overall algorithm. For validation, the strategy has been successfully applied to several mixed-signal circuit examples.