A 400 mW 50-380 MHz CMOS programmable clock recovery circuit

A high-speed programmable phase-locked loop (PLL) for clock extraction and is presented. This circuit has been manufactured in a 0.8 um CMOS process. The programmable clock recovery PLL can recover a clock from NRZ random data up to 380 Mb/s at which the power consumption is 400 mW from a single 5 volt supply. The chip requires only an external standard crystal to work. Typical performance yields an output clock with peak-to-peak jitter of 6 degree for random data input at 380 Mb/s.

[1]  Shinichi Kojima,et al.  A BiCMOS PLL-based data separator circuit with high stability and accuracy , 1991 .

[2]  Charles G. Sodini,et al.  A 200 MHz CMOS phase-locked loop with dual phase detectors , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

[3]  E. L. Hudson,et al.  A variable delay line PLL for CPU-coprocessor synchronization , 1988 .

[4]  M. G. Johnson,et al.  A Variable Delay Line Phase Locked Loop For Cpu-coprocessor Synchronization , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

[5]  Tae-Ju Lee,et al.  A 155-MHz clock recovery delay- and phase-locked loop , 1992 .