Compiling and optimizing image processing algorithms for FPGAs

This paper presents a high-level language for expressing image processing algorithms, and an optimizing compiler that targets FPGAs. The language is called SA-C, and this paper focuses on the language features that 1) support image processing, and 2) enable efficient compilation to FPGAs. It then describes the compilation process, in which SA-C algorithms are translated into non-recursive data flow graphs, which in turn are translated into VHDL. Finally, it presents performance numbers for some well-known image processing routines, written in SAC and automatically compiled to an Annapolis Microsystems WildForce board with Xilinx 4036XL FPGAs.

[1]  André DeHon,et al.  The Density Advantage of Configurable Computing , 2000, Computer.

[2]  John Woodfill,et al.  Real-time stereo vision on the PARTS reconfigurable computer , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[3]  Jorge Cabrera-Gámez,et al.  Reactive Computer Vision System with Reconfigurable Architecture , 1999, ICVS.

[4]  Bruce A. Draper,et al.  Sassy: A Language and Optimizing Compiler for Image Processing on Reconfigurable Computing Systems , 1999, ICVS.

[5]  E. M. Hartwell.  Boston , 1906 .

[6]  Thomas M. Lahey,et al.  Fortran 90 programming , 1994 .

[7]  Pietro Perona,et al.  Real-time 2-D feature detection on a reconfigurable computer , 1998, Proceedings. 1998 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (Cat. No.98CB36231).

[8]  Bruce A. Draper,et al.  Compiling image processing applications to reconfigurable hardware , 2000, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors.