Compact circuit simulation model of silicon carbide static induction and junction field effect transistors

The electrical characterization and model development for silicon carbide (SiC) vertical channel SIT and JFET structures are presented in this work. A compact model is developed based on the device geometry and SiC material properties. The model is validated against measured data at 25/spl deg/C and 100/spl deg/C for a prototype 0.03 cm/sup 2/ SiC SIT provided by Northrop Grumman. Validation is also done against the power JFET present in the combined MOSFET-SiC JFET cascode structure from SiCED. The model's on-state and transient characteristics are validated over this temperature range. Validation of the model shows excellent agreement with measured data. The physics-based approach implemented in this model is crucial to describing the transient behavior over a wide range of application conditions and temperature ranges.

[1]  H. Zirath,et al.  An empirical-table based FET model , 1999, 1999 IEEE MTT-S International Microwave Symposium Digest (Cat. No.99CH36282).

[2]  Anne Henry,et al.  SiC power devices for high voltage applications , 1999 .

[3]  B. J. Baliga,et al.  Modern Power Devices , 1987 .

[4]  P. A. Orphanos,et al.  High power 4H-SiC static induction transistors , 1995, Proceedings of International Electron Devices Meeting.

[6]  Homer Alan Mantooth,et al.  Silicon carbide PiN and merged PiN Schottky power diode models implemented in the Saber circuit simulator , 2004 .

[7]  G. Griepentrog,et al.  Modeling of silicon carbide (SiC) power devices for electronic switching in low voltage applications , 2004, 2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551).