A CAD framework for generating self-checking multipliers based on residue codes
暂无分享,去创建一个
[1] JeawLouis DUFOUR. Safety computations in integrated circuits , 1996, Proceedings of 14th VLSI Test Symposium.
[2] Earl E. Swartzlander,et al. Computer Arithmetic , 1980 .
[3] Michael Nicolaidis,et al. Efficient implementations of self-checking adders and ALUs , 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.
[4] Algirdas Avizienis,et al. Arithmetic Algorithms for Error-Coded Operands , 1973, IEEE Transactions on Computers.
[5] Yervant Zorian,et al. Fault-secure shifter design: results and implementations , 1997, Proceedings European Design and Test Conference. ED & TC 97.
[6] Michael Nicolaidis,et al. Fault-Secure Parity Prediction Arithmetic Operators , 1997, IEEE Des. Test Comput..
[7] W. W. Peterson,et al. Error-Correcting Codes. , 1962 .
[8] Frederick F. Sellers,et al. Error detecting logic for digital computers , 1968 .
[9] D. Nikolos,et al. Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes , 1988, IEEE Trans. Computers.
[10] Yervant Zorian,et al. Scaling deeper to submicron: on-line testing to the rescue , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).
[11] Israel Koren. Computer arithmetic algorithms , 1993 .
[12] Stanislaw J. Piestrak,et al. Design of residue generators and multioperand modular adders using carry-save adders , 1991, [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic.
[13] Tack-Don Han,et al. Fast area-efficient VLSI adders , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).
[14] Michael Nicolaidis,et al. On-line testing for VLSI: state of the art and trends , 1998, Integr..
[15] Michael Nicolaidis,et al. Achieving fault secureness in parity prediction arithmetic operators: general conditions and implementations , 1996, Proceedings ED&TC European Design and Test Conference.
[16] H. T. Kung,et al. A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.
[17] Eberhard Böhl,et al. The fail-stop controller AE11 , 1997, Proceedings International Test Conference 1997.
[18] Kai Hwang,et al. Computer arithmetic: Principles, architecture, and design , 1979 .
[19] Uwe Sparmann,et al. On the check base selection problem for fast adders , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.
[20] Jack Sklansky,et al. Conditional-Sum Addition Logic , 1960, IRE Trans. Electron. Comput..
[21] D. A. Anderson,et al. Design of self-checking digital networks using coding techniques , 1971 .
[22] Michael Nicolaidis. Scaling deeper to submicron: on-line testing to the rescue , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[23] Harold S. Stone,et al. A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.
[24] Sudhakar M. Reddy,et al. On the effectiveness of residue code checking for parallel two's complement multipliers , 1994, Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing.
[25] Michael Nicolaidis. Design for soft-error robustness to rescue deep submicron scaling , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).