On accurate modeling and efficient simulation of CMOS opens

This paper presents a new modeling and simulation technique for CMOS opens. The significance of the method is that both the hazard and charge-sharing effects of all possible opens are modeled in terms of a set of detecting conditions. They are efficiently represented at logic level. Then during fault simulations only these detecting conditions are evaluated to decide if the opens are detected. In this way, all efficient simulation techniques developed at logic level can be applied. The paper shows how the detecting conditions are derived for arbitrary opens. Results of a parallel pattern simulator show a good trade-off of accuracy versus efficiency.<<ETX>>

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