Design of hashtable for heterogeneous architectures

This work presents a hybrid hashtable which targets the SoC composed of a CPU and integrated GPU. The presented design uses as a first stage the integrated GPU, in a multi level bounded linear probing technique, followed by a second stage CPU cuckoo insertion. The two stages are performed in a complementary pipelined manner, are each suited for the device they run on and attain good insert and get performance. The solution is implemented using the Intel DPC++ standard, an extension of the Khronos SyCL standard and tested with the Intel SoC GEN11 architecture. Details of the implementation and the Intel GEN architecture are also presented.