VHDL and Key Important Constructs

This chapter discusses the key important VHDL constructs. VHDL a is hardware description language and consists of many powerful concurrent and sequential constructs. The key concurrent and sequential constructs are used to describe the design functionality to generate intended hardware. These constructs include process, when else, with select, if then else case, signal and variable declarations and assignments. Even this chapter discusses the important constructs like wait, wait on, wait for, wait until, for loop, and while loop. This chapter is useful for RTL design engineers to understand the VHDL coding styles and synthesizable VHDL. This chapter covers the practical illustrations for every construct. The explanation is given for every synthesizable VHDL code with the synthesis results. This can be useful while working in the FPGA as well as ASIC design domains.