PROBE: a PPSFP simulator for resistive bridging faults

Bridging faults in CMOS circuits are usually modeled as a wired-OR, wired-AND, or small fixed resistance. Real bridging faults have a resistance distribution ranging from very small to quite large. The parametric model has been proposed to handle this resistance distribution, along with table-oriented approaches that are accurate and fast. Fault simulators and a test generator have been developed using these models. Prior approaches were too slow to simulate or generate large test sets, handle large circuits, or analyze a wide variety of different test sets. We have developed PROBE, A PSEUDO-PPSFP simulator for resistive bridging faults that is significantly faster while maintaining circuit-level accuracy. We have used PROBE to analyze several large test sets on the ISCAS85 circuits in an effort to gain insight into how existing test generation approaches detect resistive bridges.

[1]  Michel Renovell,et al.  The concept of resistance interval: a new parametric model for realistic resistive bridging fault , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[2]  Rosa Rodríguez-Montañés,et al.  Bridging defects resistance measurements in a CMOS process , 1992, Proceedings International Test Conference 1992.

[3]  S. Oostdijk,et al.  Realistic defect coverages of voltage and current tests , 1996, Digest of Papers 1996 IEEE International Workshop on IDDQ Testing.

[4]  John Paul Shen,et al.  Inductive Fault Analysis of MOS Integrated Circuits , 1985, IEEE Design & Test of Computers.

[5]  Jochen A. G. Jess,et al.  An efficient CMOS bridging fault simulator: with SPICE accuracy , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Yuyun Liao,et al.  Optimal voltage testing for physically-based faults , 1996, Proceedings of 14th VLSI Test Symposium.

[7]  Michel Renovell,et al.  Bridging fault coverage improvement by power supply control , 1996, Proceedings of 14th VLSI Test Symposium.

[8]  Kuen-Jong Lee,et al.  BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults , 1999, TODE.

[9]  M. Ray Mercer,et al.  REDO-random excitation and deterministic observation-first commercial experiment , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[10]  Michele Favalli,et al.  Parametric Bridging Fault Characterieation for the Fault Simulation of Library-Based ICs , 1992, Proceedings International Test Conference 1992.

[11]  Janak H. Patel,et al.  Fast and accurate CMOS bridging fault simulation , 1993, Proceedings of IEEE International Test Conference - (ITC).

[12]  Steven D. Millman,et al.  AN ACCURATE BRIDGING FAULT TEST PATTERN GENERATOR , 1991, 1991, Proceedings. International Test Conference.

[13]  Dong Sam Ha,et al.  AN EFFICIENT, FORWARD FAULT SIMULATION ALGORITHM BASED ON THE PARALLEL PATTERN SINGLE FAULT PROPAGAT , 1991, 1991, Proceedings. International Test Conference.

[14]  João Paulo Teixeira,et al.  IC DEFECTS-BASED TESTABILITY ANALYSIS , 1991, 1991, Proceedings. International Test Conference.

[15]  Robert C. Aitken,et al.  Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds , 1993, Proceedings of IEEE International Test Conference - (ITC).

[16]  D. M. H. Walker,et al.  Accurate fault modeling and fault simulation of resistive bridges , 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

[17]  Michel Renovell,et al.  CMOS bridging fault modeling , 1994, Proceedings of IEEE VLSI Test Symposium.

[18]  D. M. H. Walker,et al.  Resistive bridge fault modeling, simulation and test generation , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).