Error Correction Codes for SEU and SEFI Tolerant Memory Systems

In this paper a modification of the Hsiao SEC-DED (Single Error Correction, Double Error Detection) code is presented. The proposed code is still a SEC-DED code, but it is also able to correct a byte erasure. This code has been developed to protect the memory chips of a spaceborne computer against SEU (Single Event Upset) and SEFI (Single Event Functional Interruption) faults. The code rate of our proposed code is the same of the Hsiao code and is particularly suitable for byte organized 64-bits memory systems. In fact, for these systems a (72,64) code can be constructed and a memory organization based on nine chips can be designed. The byte erasure correction allows to tolerate the occurrence of a SEFI fault in one of the memory chips without data loss.

[1]  J.M. Benedetto,et al.  Extreme latchup susceptibility in modern commercial-off-the-shelf (COTS) monolithic 1M and 4M CMOS static random-access memory (SRAM) devices , 2005, IEEE Radiation Effects Data Workshop, 2005..

[2]  M. Shea,et al.  CREME96: A Revision of the Cosmic Ray Effects on Micro-Electronics Code , 1997 .

[3]  Jien-Chung Lo,et al.  Erasure error correction with hardware detection , 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

[4]  E. Normand.  Single-event effects in avionics , 1996 .

[5]  Michael Nicolaidis,et al.  SEU-tolerant SRAM design based on current monitoring , 1994, Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing.

[6]  D.N. Nguyen,et al.  Single Event Effect Characterization of High Density Commercial NAND and NOR Nonvolatile Flash Memories , 2007, IEEE Transactions on Nuclear Science.

[7]  Fabrizio Lombardi,et al.  A Comparative Evaluation of Designs for Reliable Memory Systems , 2005, J. Electron. Test..

[8]  Allan H. Johnston,et al.  The influence of VLSI technology evolution on radiation-induced latchup in space systems , 1996 .

[9]  F. Irom,et al.  Space processor radiation mitigation and validation techniques for an 1,800 MIPS processor board , 2003, Proceedings of the 7th European Conference on Radiation and Its Effects on Components and Systems, 2003. RADECS 2003..

[10]  M. Y. Hsiao,et al.  A class of optimal minimum odd-weight-column SEC-DED codes , 1970 .

[11]  J.L. Massey,et al.  Theory and practice of error control codes , 1986, Proceedings of the IEEE.

[12]  Carl-Erik W. Sundberg,et al.  A Reliable Spaceborne Memory with a Single Error and Erasure Correction Scheme , 1979, IEEE Transactions on Computers.

[13]  Allan H. Johnston,et al.  A new class of single event hard errors [DRAM cells] , 1994 .

[14]  J.M. Soden.  I/sub DDQ/ testing for submicron CMOS IC technology qualification , 1997, Digest of Papers IEEE International Workshop on IDDQ Testing.

[15]  Paul E. Dodd,et al.  Neutron-induced latchup in SRAMs at ground level , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[16]  H. Saito,et al.  Neutron-induced SEU in bulk and SOI SRAMS in terrestrial environment , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[17]  R. Harboe-Sorensen,et al.  Heavy-Ion SEE Test Concept and Results for DDR-II Memories , 2007, IEEE Transactions on Nuclear Science.

[18]  C.W. Slayman,et al.  Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations , 2005, IEEE Transactions on Device and Materials Reliability.

[19]  P.E. Dodd,et al.  Neutron-induced soft errors, latchup, and comparison of SER test methods for SRAM technologies , 2002, Digest. International Electron Devices Meeting,.