Optimized model checking of multiple properties

This paper addresses the problem of model checking multiple properties on the same circuit/system. Although this is a typical scenario in several industrial verification frameworks, most model checkers currently handle single properties, verifying multiple properties one at a time. Possible correlations and shared sub-problems, that could be considered while checking different properties, are typically ignored, either for the sake of simplicity or for Cone-Of-Influence minimization. In this paper we describe a preliminary effort oriented to exploit possible synergies among distinct verification tasks of several properties on the same circuit. Besides considering given sets of properties, we also show that multiple properties can be automatically extracted from individual properties, thus simplifying difficult model checking tasks. Preliminary experimental results indicate that our approach can lead to significant performance improvements.

[1]  L Michael,et al.  Inductively Finding a Reachable State Space Over-Approximation , 2006 .

[2]  Koen Claessen,et al.  SAT-Based Verification without State Space Traversal , 2000, FMCAD.

[3]  Mary Sheeran,et al.  Checking Safety Properties Using Induction and a SAT-Solver , 2000, FMCAD.

[4]  Aaron R. Bradley,et al.  SAT-Based Model Checking without Unrolling , 2011, VMCAI.

[5]  Mingsong Chen,et al.  Synchronized Generation of Directed Tests Using Satisfiability Solving , 2010, 2010 23rd International Conference on VLSI Design.

[6]  Kenneth L. McMillan,et al.  Interpolation and SAT-Based Model Checking , 2003, CAV.

[7]  Edmund M. Clarke,et al.  Symbolic Model Checking: 10^20 States and Beyond , 1990, Inf. Comput..

[8]  Gianpiero Cabodi,et al.  Speeding up model checking by exploiting explicit and hidden verification constraints , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[9]  Sérgio Vale Aguiar Campos,et al.  Compositional Reasoning in Model Checking , 1997, COMPOS.

[10]  Shahid Ikram,et al.  Accelerated verification of RTL assertions based on satisfiability solvers , 2002, Seventh IEEE International High-Level Design Validation and Test Workshop, 2002..

[11]  Zurab Khasidashvili,et al.  Simultaneous SAT-Based Model Checking of Safety Properties , 2005, Haifa Verification Conference.

[12]  Gianpiero Cabodi,et al.  Partitioning Interpolant-Based Verification for Effective Unbounded Model Checking , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.