The quarter-state-sequence floorplan representation

A floorplan of a bounding box is its dissection into rectangles (rooms) by horizontal and vertical segments. This paper proposes a string data structure called the Quarter-state sequence (or Q sequence) to represent the floorplan. The Q sequence is a concatenation of the states of rooms along the Abe order and is related to the VH graph, which is the union of the vertical-constraint and horizontal-constraint graphs. It is proved that any floorplan of n rooms is uniquely encoded by a Q sequence and any Q sequence is uniquely decoded to a floorplan, both in O(n) time. An exact formula for counting distinct floorplans is given and compared with existing bounds. A linear time transformation of one Q sequence to another is defined. An n-room packing algorithm based on simulated annealing was implemented and found to compare favorably with existing packing algorithms.

[1]  Yen-Tai Lai,et al.  A theory of rectangular dual graphs , 1990, Algorithmica.

[2]  Evangeline F. Y. Young,et al.  Slicing floorplans with boundary constraints , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  K. Fujiyoshi,et al.  Simulated annealing search through general structure floorplans using sequence-pair , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[4]  Ralph H. J. M. Otten,et al.  Automatic Floorplan Design , 1982, 19th Design Automation Conference.

[5]  Yao-Wen Chang,et al.  B*-Trees: a new representation for non-slicing floorplans , 2000, DAC.

[6]  Sartaj Sahni,et al.  A linear algorithm to find a rectangular dual of a planar triangulated graph , 1986, 23rd ACM/IEEE Design Automation Conference.

[7]  Yici Cai,et al.  Corner block list: an effective and efficient topological representation of non-slicing floorplan , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[8]  Yoji Kajitani,et al.  The quarter-state sequence (Q-sequence) to represent the floorplan and applications to layout optimization , 2000, IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394).

[9]  Martin D. F. Wong,et al.  Floorplan design of VLSI circuits , 2005, Algorithmica.

[10]  Jun Gu,et al.  ECBL: an extended corner block list with solution space including optimum placement , 2001, ISPD '01.

[11]  Tamás Roska,et al.  IEEE Transactions on Circuits and Systems I - Fundamental Theory and Applications: Editorial , 2003 .

[12]  Yoji Kajitani,et al.  Module packing based on the BSG-structure and IC layout applications , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Shoji Shinoda,et al.  A condition for a maximal planar graph to have a unique rectangular dual and its application to VLSI floor-plan , 1989, IEEE International Symposium on Circuits and Systems,.

[14]  T. Takahashi,et al.  A new encoding scheme for rectangle packing problem , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

[15]  Takeshi Yoshimura,et al.  An O-tree representation of non-slicing floorplan and its applications , 1999, DAC '99.

[16]  Yao-Wen Chang,et al.  TCG: a transitive closure graph-based representation for non-slicing floorplans , 2001, DAC '01.

[17]  Ronald L. Graham,et al.  Revisiting floorplan representations , 2001, ISPD '01.

[18]  Evangeline F. Y. Young,et al.  Twin binary sequences: a non-redundant representation for general non-slicing floorplan , 2002, ISPD '02.

[19]  Yoji Kajitani,et al.  VLSI module placement based on rectangle-packing by the sequence-pair , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Yoji Kajitani,et al.  A mapping from sequence-pair to rectangular dissection , 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.