Sampled-data IIR filtering using time-mode signal processing circuits

The design of a second-order low-pass IIR filter based on time-mode signal processing circuits is presented. The filter is implemented using a set of building blocks that perform basic mathematical operations in the time-domain including time addition, weighted delayed time addition and subtraction, and unit delay. A second-order low-pass Chebyshev filter was designed in a 0.18 µm CMOS process. Simulation results confirmed that the design can achieve low-pass filtering, providing a maximum SNR of 63.6 dB and SNDR of 44.1 dB.

[1]  Gordon W. Roberts,et al.  Delta-Sigma Analog-to-Digital Conversion via Time-Mode Signal Processing , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[2]  John G. Harris,et al.  Time-based arithmetic using step functions , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[3]  Heemin Y. Yang.  A time-based energy-efficient analog-to-digital converter , 2005, IEEE Journal of Solid-State Circuits.

[4]  Gordon W. Roberts,et al.  Process-insensitive modulated-clock voltage comparator , 2006, 2006 IEEE International Symposium on Circuits and Systems.