Fast Hardware Implementations of P Systems

In this article we present the design of a fast hardware simulator for P systems using the field-programmable gate array (FPGA) technology. The simulator is non-deterministic and it uses a constant time procedure to choose one of the computational paths. The obtained strategy is fair and it is based on a pre-computation of all possible rule applications. This pre-computation is obtained by using the representation of all possible multisets of rules' applications as context-free languages. Then using a standard technique involving formal power series it is possible to obtain the generating series of corresponding languages that permits to construct the structure representing all possible rule applications for any configuration. We give a hardware design implementing some concrete examples and present the obtained results which feature an important speed-up.

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