An Area-efficient Survivor Path Architecture For Viterbi Decoders
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[1] Kumar Ramaswamy,et al. A fully integrated digital demodulation and forward error correction IC for digital satellite television , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.
[2] D.A. Luthi,et al. A single-chip concatenated FEC decoder , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.
[3] Jens Sparsø,et al. An area-efficient path memory structure for VLSI implementation of high speed Viterbi decoders , 1991, Integr..
[4] Teresa H. Y. Meng,et al. Hybrid survivor path architectures for Viterbi decoders , 1993, 1993 IEEE International Conference on Acoustics, Speech, and Signal Processing.
[5] G. Edwards. A 45-Mbits/sec. VLSI Viterbi decoder for digital video applications , 1993, Conference Proceedings National Telesystems Conference 1993.
[6] P. Glenn Gulak,et al. Architectural tradeoffs for survivor sequence memory management in Viterbi decoders , 1993, IEEE Trans. Commun..