A class of parallel architectures for fast Fourier transform

We propose a new class of parallel architectures called unfolded swapped networks (USN) for fast Fourier transform (FFT) and related problems. The VLSI area of a suitably constructed N(log/sub 2/ N+o(log N))-node USN is no more than N/sup 2/+o(N/sup 2/), which is smaller than the best known result for a log, N-dimensional butterfly network. USNs can be constructed using small butterfly modules, each built on a chip, and requires fewer pins than a similar-sized butterfly network by a factor of /spl Theta/(log N). N-point FFT can be executed on a USN at a speed comparable to a butterfly network, assuming constant link delay; it can be executed on a USN considerably faster than on a butterfly when link delay increases with length and/or when inter-chip data transfers are much slower than intra-chip ones.