Using TMR Architectures for SoC Yield Improvement

Manufacturing processes in the nanoscale era are less and less reliable thus leading to lower and lower yields. To address this problem during SoC development, memory cores are built with hardware redundancies. On the other hand, logic cores embedded in SoC usually do not have these main capabilities. Therefore, manufacturing defects affecting these cores decrease the yield of the entire SoC. Consequently, meaningful techniques for SoC yield improvement must also consider logic cores. In this paper, we propose and investigate the usage of TMR architectures for logic cores to increase the overall SoC yield. We also propose a solution to improve the fault tolerance of TMR architectures. Results obtained on SoC examples (ISCAS’85 and ITC’99 benchmark circuits as logic cores merged with memory cores at different rates) demonstrate the interest of using TMR architectures for logic cores for SoC yield enhancement.