A lower power sigma delta modulator for GSM and W-CDMA applications

This work presents a low power cascaded sigma-delta modulator (SDM) for W-CDMA and GSM dual bandwidth applications. This proposed SDM has the characteristics of side bandwidth for W-CDMA applications and has low noise floor in the lower frequency band for GSM applications. Low-distortion swing-suppressing SDM and interpolative SDM cascaded units are used in this modulator. The low-distortion technique has the swing-suppressing characteristic, and it can reduce the power consumption and the resolution can be improved even under non-linearity effects. We also optimize the architecture to reduce the components to reduce the power consumption. The circuit is implemented in a standard 0.18-μm 1P6M CMOS technology. For the W-CDMA applications, the measurements indicate a dynamic range of 68 dB and a SNDR of 61 dB. For the GSM applications, the measurements indicate a dynamic range 76 dB and a SNDR of 70 dB. The core area is 0.84 mm2, the power consumption is 28-mW at 1.8 V.

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