A 16-channel digital TDC chip

Abstract A 16-channel digital TDC chip has been built for the DIRC Cherenkov counter of the BaBar experiment at the SLAC B-factory (Stanford, USA). The binning is 0.5 ns and the full-scale 32 ms. The data-driven architecture integrates channel buffering and selective readout of data falling within a programmable time window. The linearity is better than 80 ps r.m.s. on 90% of the production parts.