Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits Using SPICE Simulation

This work examines the metal-ferroelectric-insulator-semiconductor (MFIS) negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. With the aid of a short-channel NC-FinFET compact model, we confirm the functionality and determine the standby-power/switching-energy/delay performance of logic circuits (5-stage inverter and 4-bit Manchester carry-chain (MCC) adder) employing 14nm ULP NC-FinFETs versus FinFETs. We show that the inverse $V_{ds}$-dependency of threshold voltage $(V_{T})$, also known as the negative DIBL, of NCFET is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low $V_{DD}$.