A Parallel Full-System Emulator for Risc Architure Host

In this paper, we port a parallel full-system emulator to RISC host to achieve higher performance by utilize all the multi-core resources from physical CPU, in contrast the traditional full-system emulator is sequentially in SMP emulation and can only use one core of host machine. We mainly deal with the atomic instruction translation to RISC ll/sc pairs, and apply lightweight lock-free FIFO queue algorithms using both interleaving and non-interleaving ll/sc pairs. The tests show that the performance of parallel full-system emulator have high efficiency.

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