Common-source-line array

Traditional array organization of bipolar nonvolatile memories such as STT-MRAM and memristor utilizes two bitlines for cell manipulations. With technology scaling, such bitline pair will soon become the bottleneck for further density improvement. In this article we propose a novel common-source-line array architecture, which uses a shared source-line along the row, leaving only one bitline per column. We elaborate the array design to ensure reliability, and demonstrate its effectiveness on STT-MRAM and memristor memory arrays. Our study results show that with comparable latency and energy, the proposed common-source-line array can save 34% and 33% area for Memristor-RAM and STT-MRAM respectively, compared with corresponding dual-bitline arrays.

[1]  C. Hu.  Gate oxide scaling limits and projection , 1996 .

[2]  M. Yoshida,et al.  An embedded 0.405 /spl mu/m/sup 2/ stacked DRAM technology integrated with high-performance 0.2 /spl mu/m CMOS logic and 6-level metalization , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[3]  H.L. Ho,et al.  A simple and high-performance 130 nm SOI eDRAM technology using floating-body pass-gate transistor in trench-capacitor cell for system-on-a-chip (SoC) applications , 2003, IEEE International Electron Devices Meeting 2003.

[4]  N. Sakimura,et al.  A 512kb cross-point cell MRAM , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[5]  M. Kund,et al.  Status and outlook of emerging nonvolatile memory technologies , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[6]  R. Symanczyk,et al.  Conductive bridging RAM (CBRAM): an emerging non-volatile memory technology scalable to sub 20nm , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[7]  K. Shakeri,et al.  Compact physical IR-drop models for chip/package co-design of gigascale integration (GSI) , 2005, IEEE Transactions on Electron Devices.

[8]  M. Hosomi,et al.  A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[9]  Shoji Ikeda,et al.  2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[10]  Byung-Gil Choi,et al.  A 0.1-$\mu{\hbox {m}}$ 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation , 2007, IEEE Journal of Solid-State Circuits.

[11]  D. Stewart,et al.  The missing memristor found , 2008, Nature.

[12]  S. Takahashi,et al.  Lower-current and fast switching of a perpendicular TMR for high speed and high density spin-transfer-torque MRAM , 2008, 2008 IEEE International Electron Devices Meeting.

[13]  Yu (Kevin) Cao,et al.  What is Predictive Technology Model (PTM)? , 2009, SIGD.

[14]  Peng Li,et al.  Nonvolatile memristor memory: Device characteristics and design implications , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[15]  Yuichi Ito,et al.  A 90nm 12ns 32Mb 2T1MTJ MRAM , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[16]  Yiran Chen,et al.  An overview of non-volatile memory technology and the implication for tools and architectures , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[17]  J. Yang,et al.  Electrical transport and thermometry of electroformed titanium dioxide memristive switches , 2009 .

[18]  Yiran Chen,et al.  A novel architecture of the 3D stacked MRAM L2 cache for CMPs , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[19]  Erik Nelson,et al.  A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[20]  Fatih Hamzaoglu,et al.  Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process , 2010, IEEE Journal of Solid-State Circuits.

[21]  A. Driskill-Smith,et al.  Fully integrated 54nm STT-RAM with the smallest bit cell dimension for high density memory application , 2010, 2010 International Electron Devices Meeting.

[22]  Shoji Ikeda,et al.  A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme , 2010, IEEE Journal of Solid-State Circuits.

[23]  William Song,et al.  Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[24]  Yoshihiro Ueda,et al.  A 64Mb MRAM with clamped-reference and adequate-reference schemes , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).