Based On-line Testing and Recovery for Critical Digital Systems

This work proposes a Genetic Algorithm (GA) based on-line testing and recovery mechanism for reconfigurable critical digital circuits. Given the input / output specifications for a circuit, multiple versions (n) of the circuit are evolved using GA techniques. The n different versions are evolved to provide 100% fault coverage. A TMR fault tolerant circuit is designed using three different versions out of these ‘n’ versions and a voting mechanism that chooses the majority output. Continuous on-line testing/fault detection is achieved by systematically changing the version used in the three modules. This is done so as to exercise all the components present in the modules. As one fault-free circuit provides the output, the external software control downloads the new configuration of a different version on to one of the other two circuits for testing. This process is cyclically repeated between the three circuits, with the various versions being periodically downloaded and tested, thus covering all the components. During the period of download, only one of the circuits is out of action and so the output of the circuit is not affected. Once a fault is detected, the faulty version is replaced with a fault-free version and the process continues. The efficacy of the proposed technique has been studied using simulated faults and hardware implementation of a 2*2 multiplier as a proof of concept. It is found that the proposed technique provides on-line self-testing and recovery of 100% single component failures.

[1]  Andy M. Tyrrell,et al.  A hardware immune system for benchmark state machine error detection , 2002, Proceedings of the 2002 Congress on Evolutionary Computation. CEC'02 (Cat. No.02TH8600).

[2]  Gunnar Tufte,et al.  Prototyping a GA Pipeline for complete hardware evolution , 1999, Proceedings of the First NASA/DoD Workshop on Evolvable Hardware.

[3]  Steven A. Guccione,et al.  GeneticFPGA: evolving stable circuits on mainstream FPGA devices , 1999, Proceedings of the First NASA/DoD Workshop on Evolvable Hardware.

[4]  Andrew M. Tyrrell,et al.  Evolutionary strategies and intrinsic fault tolerance , 2001, Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001.

[5]  Adrian Thompson Evolving fault tolerant systems , 1995 .

[6]  Xin Yao,et al.  Promises and challenges of evolvable hardware , 1996, IEEE Trans. Syst. Man Cybern. Part C.

[7]  Julian Francis Miller,et al.  Evolution of Digital Filters Using a Gate Array Model , 1999, EvoWorkshops.

[8]  Jordi Madrenas,et al.  Evolvable Systems: From Biology to Hardware , 1996, Lecture Notes in Computer Science.

[9]  Vidroha Debroy,et al.  Genetic Programming , 1998, Lecture Notes in Computer Science.

[10]  Irith Pomeranz,et al.  On improving genetic optimization based test generation , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[11]  Marley M. B. R. Vellasco,et al.  Evolvable Systems in Hardware Design: Taxonomy, Survey and Applications , 1996, ICES.

[12]  Adrian Stoica,et al.  Fault-tolerant evolvable hardware using field-programmable transistor arrays , 2000, IEEE Trans. Reliab..

[13]  M. Sipper,et al.  Toward robust integrated circuits: The embryonics approach , 2000, Proceedings of the IEEE.

[14]  Daniel P. Siewiorek,et al.  Reliable Computer Systems: Design and Evaluation, Third Edition , 1998 .

[15]  Andy M. Tyrrell,et al.  Evolved fault tolerance in evolvable hardware , 2002, Proceedings of the 2002 Congress on Evolutionary Computation. CEC'02 (Cat. No.02TH8600).

[16]  Zbigniew Michalewicz,et al.  Genetic Algorithms + Data Structures = Evolution Programs , 1992, Artificial Intelligence.

[17]  A. P. Shanthi,et al.  AUTOMATIC GA BASED EVOLUTION OF FAULT TOLERANT DIGITAL CIRCUITS , 2002 .

[18]  Andrew M. Tyrrell,et al.  The architecture for a hardware immune system , 2001, Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001.