Detectability of CMOS stuck-open faults using random and pseudorandom test sequences
暂无分享,去创建一个
[1] Sunil Jain,et al. Statistical Fault Analysis , 1985, IEEE Design & Test of Computers.
[2] Gary S. Ditlow,et al. Random Pattern Testability , 1984, IEEE Transactions on Computers.
[3] Edward J. McCluskey,et al. Pseudorandom Testing , 1987, IEEE Transactions on Computers.
[4] Ranjan Roy,et al. Binomial identities and hypergeometric series , 1986 .
[5] Edward McCluskey,et al. Built-In Self-Test Structures , 1985, IEEE Design & Test of Computers.
[6] Jacob Savir,et al. Random Pattern Testability of Delay Faults , 1988, IEEE Trans. Computers.
[7] Sudhakar M. Reddy,et al. Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits , 1986, IEEE Transactions on Computers.
[8] Edward McCluskey,et al. Built-In Self-Test Techniques , 1985, IEEE Design & Test of Computers.
[9] Shedletsky,et al. The Error Latency of a Fault in a Sequential Digital Circuit , 1976, IEEE Transactions on Computers.
[10] R. L. Wadsack,et al. Fault modeling and logic simulation of CMOS and MOS integrated circuits , 1978, The Bell System Technical Journal.
[11] Stephen Y. H. Su,et al. Fault Diagnosis of MOS Combinational Networks , 1982, IEEE Transactions on Computers.
[12] Y.M. Elzig. Automatic Test Generation for Stuck-Open Faults in CMOS VLSI , 1981, 18th Design Automation Conference.
[13] Jacob Savir,et al. On Random Pattern Test Length , 1984, IEEE Transactions on Computers.
[14] J. Mucha,et al. Built-In Test for Complex Digital Integrated Circuits , 1979, Fifth European Solid State Circuits Conference - ESSCIRC 79.