Proper Electrostatic Modulation of Electric Field in a Reliable Nano-SOI With a Developed Channel

This brief is describing a useful idea to reform the distribution of the electric field for nanosilicon-on-insulator metal–oxide–semiconductors-field-effect transistors. The approach we benefit from it is to develop a part of the channel region into the drain region. This technique modulates the channel charge with the creation of an extra peak electric field in the developed channel/drain region interface. As a result, critical electric field of the new proposed structure at the end of the channel is successfully mitigated. DC and ac investigations revealed that the novel device has more reliability than a common device widely utilized in today’s industry. The evaluation of both the common and proposed structures is handled by ATLAS simulator from SILVACO family. The important parameters in the cases of the short-channel effects, hot-carrier effects, switching speed, power gain, and parasitic capacitances are comprehensively studied to attain the best decision about the excellent electrical performance of the proposed device.

[1]  Meysam Zareiee.  Modifying Buried Layers in Nano-MOSFET for Achieving Reliable Electrical Characteristics , 2016 .

[2]  T. Tsuchiya,et al.  Experimental 0.25-/spl mu/m-gate fully depleted CMOS/SIMOX process using a new two-step LOCOS isolation technique , 1995 .

[3]  A. Orouji,et al.  Improvement of Electrical Properties in a Novel Partially Depleted SOI MOSFET With Emphasizing on the Hysteresis Effect , 2013, IEEE Transactions on Electron Devices.

[4]  A. Orouji,et al.  Stopping electric field extension in a modified nanostructure based on SOI technology - A comprehensive numerical study , 2017 .

[5]  M. Zareiee,et al.  A novel high performance nano-scale MOSFET by inserting Si3N4 layer in the channel , 2015 .

[6]  Saba Rajabi,et al.  A novel partial SOI LDMOSFET with periodic buried oxide for breakdown voltage and self heating effect enhancement , 2015 .

[7]  M. Fathipour,et al.  Improvement of electrical performance in junctionless nanowire TFET using hetero-gate-dielectric , 2017 .

[8]  Chieh-Lin Wu,et al.  I-Gate Body-Tied Silicon-on-Insulator MOSFETs With Improved High-Frequency Performance , 2011, IEEE Electron Device Letters.

[9]  Ali Afzali-Kusha,et al.  Ground plane fin-shaped field effect transistor (GP-FinFET): A FinFET for low leakage power circuits , 2012 .

[10]  A. Orouji,et al.  High-Voltage and RF Performance of SOI MESFET Using Controlled Electric Field Distribution , 2012, IEEE Transactions on Electron Devices.

[11]  L. Selmi,et al.  Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology application , 2001 .

[12]  Vishwas Jaju,et al.  Silicon-on-Insulator Technology , 2004 .