A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS
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Takayuki Shibasaki | Hirotaka Tamura | Ali Sheikholeslami | Joshua Liang | Danny Yoo | Hisakatsu Yamaguchi | Wahid Rahman
[1] J.D.H. Alexander. Clock recovery from random binary signals , 1975 .
[2] Tejasvi Anand,et al. 8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).
[3] K. Mueller,et al. Timing Recovery in Digital Synchronous Data Receivers , 1976, IEEE Trans. Commun..
[4] James E. Jaussi,et al. A 1.2–5Gb/s 1.4–2pJ/b serial link in 22nm CMOS with a direct data-sequencing blind oversampling CDR , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).
[5] Behzad Razavi,et al. A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector , 2003, IEEE J. Solid State Circuits.
[6] Mahyar Kargar,et al. An 8.5–11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition , 2013, IEEE Journal of Solid-State Circuits.
[7] Hirotaka Tamura,et al. A Blind Baud-Rate ADC-Based CDR , 2013, IEEE Journal of Solid-State Circuits.
[8] Pavan Kumar Hanumolu,et al. A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance , 2007, 2007 IEEE Custom Integrated Circuits Conference.
[9] Thomas Toifl,et al. A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth , 2014, IEEE Journal of Solid-State Circuits.
[10] Hugh Mair,et al. Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2Vpp voltage-mode driver , 2011, 2011 IEEE International Solid-State Circuits Conference.
[11] Hirotaka Tamura,et al. An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection , 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.
[12] Ching-Yuan Yang,et al. A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With $4\times$ Oversampling , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[13] Michael M. Green,et al. An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS , 2015, IEEE Journal of Solid-State Circuits.
[14] Takayuki Shibasaki,et al. 6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).
[15] N. Tzartzanis,et al. A 40–44 Gb/s 3$\times$ Oversampling CMOS CDR/1:16 DEMUX , 2007, IEEE Journal of Solid-State Circuits.
[16] Hirotaka Tamura,et al. A 40-to-44Gb/s 3× Oversampling CMOS CDR/1:16 DEMUX , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[17] Hirotaka Tamura,et al. A Reference-Less Single-Loop Half-Rate Binary CDR , 2015, IEEE Journal of Solid-State Circuits.