A universal CMOS voltage interface circuit
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Eby G. Friedman | Radu M. Secareanu | Scott Warner | Juan Becerra | E. Friedman | R. Secareanu | Juan Becerra | S. Warner
[1] John B. Shoven,et al. I , Edinburgh Medical and Surgical Journal.
[2] L.W. Linholm,et al. An optimized output stage for MOS integrated circuits , 1975, IEEE Journal of Solid-State Circuits.
[3] Ieee Circuits,et al. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[4] Hendrikus J. M. Veendrick,et al. Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .
[5] Kjell O. Jeppson,et al. CMOS Circuit Speed and Buffer Optimization , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[6] Tetsuya Iida,et al. Highly reliable process insensitive 3.3 V-5 V interface circuit , 1992, 1992 Symposium on VLSI Circuits Digest of Technical Papers.
[7] Toshiro Takahashi,et al. A O.6p1n CMOS SOG with 5V/3.3V Interfaces , 1992 .
[8] J.S. Caravella,et al. Three volt to five volt CMOS interface circuit device leakage limited DC power dissipation , 1993, Sixth Annual IEEE International ASIC Conference and Exhibit.
[9] Baher Haroun,et al. A novel reduced swing CMOS bus interface circuit for high speed low power VLSI systems , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.
[10] Srinivasa Vemuru,et al. Short-circuit power dissipation estimation for cmos logic gates , 1994 .
[11] T. Tomita,et al. 622 Mbps 8 mW CMOS Low-Voltage Interface Circuit , 1995 .
[12] Eby G. Friedman,et al. A high speed CMOS buffer for driving large capacitive loads in digital ASICs , 1998, Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372).