A novel 3D embedded gate field effect transistor: Screen-grid FET: Device concept and modelling

Abstract A novel 3D field effect transistor on SOI – screen-grid FET (SGrFET) – is proposed and an analysis of its DC behaviour is presented by means of 2D TCAD analysis. The novel feature of the SGrFET is the design of 3D insulated gate cylinders embedded in the SOI body. This novel gate topology improves efficiency and allows great flexibility in device and gate geometry to optimize DC performance. The floating body effect is avoided and the double gating row configuration controls short channel effects. The traditional intimate relationship between gate length and source-drain distance is removed, resulting in easy control of drain induced barrier lowering, improved output conductance and ideal sub-threshold slope. The separation between the gate fingers in each row is the key factor to optimize the performance, whilst downscaling of the source-drain distance and oxide thickness is not essential from an operational point of view. The device exhibits a huge potential in low power electronics as given by an efficiency of transconductance “gm/Id” of 39 S/A at VDS = 100 mV over a large gate voltage range and at a source-drain distance of 825 nm. We present the modelling results of the influence of gate cylinder distribution in the channel, channel doping, gate oxide thickness, gate finger distance and source-drain distance on the characteristics of the device.

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