FPGA Clock Management for Low Power

Clock management circuits are relatively new FPGA architectural blocks that are critical to solving clock distribution problems associated with high-speed, high-density designs. We outline the use of three FPGA clock managers in a variety of applications, and consider their application to low-power systems which adjust clock rates based on the amount of computation needed. Dynamic clock management design problems are examined and common solutions are outlined. We propose the use of a dynamic programmable clock divider in conjunction with FPGA clock managers. An example application is also described.

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