SAT-Based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions

Introducing partial programmability in circuits by replacing some gates with look up tables (LUTs) can be an effective way to improve post-silicon or in-field rectification and debugging. Although finding configurations of LUTs that can correct the circuits can be formulated as a QBF problem, solving it by state-of-the-art QBF solvers is still a hard problem for large circuits and many LUTs. In this paper, we present a rectification and debugging method for combinational circuits with LUTs by repeatedly applying Boolean SAT solvers. Through the experimental results, we show our proposed method can quickly find LUT configurations for large circuits with many LUTs, which cannot be solved by a QBF solver.

[1]  Mikolás Janota,et al.  Abstraction-Based Algorithm for 2QBF , 2011, SAT.

[2]  Satish Narayanasamy,et al.  Patching Processor Design Errors with Programmable Hardware , 2007, IEEE Micro.

[3]  Marco Benedetti,et al.  sKizzo: A Suite to Evaluate and Certify QBFs , 2005, CADE.

[4]  Malay K. Ganai,et al.  Robust Boolean reasoning for equivalence checking and functional property verification , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Marco Benedetti,et al.  Evaluating QBFs via Symbolic Skolemization , 2005, LPAR.

[6]  Masahiro Fujita,et al.  An energy-efficient patchable accelerator for post-silicon engineering changes , 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[7]  Masahiro Fujita,et al.  Advanced Verification Techniques Based on Learning , 1995, 32nd Design Automation Conference.

[8]  Robert K. Brayton,et al.  ABC: An Academic Industrial-Strength Verification Tool , 2010, CAV.

[9]  Moayad Fahim Ali,et al.  Fault diagnosis and logic debugging using Boolean satisfiability , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Armando Tacchella,et al.  QuBE++: An Efficient QBF Solver , 2004, FMCAD.

[11]  Mikolás Janota,et al.  Solving QBF with Counterexample Guided Refinement , 2012, SAT.

[12]  Yoshida Hiroaki,et al.  Increasing Yield Using Partially-Programmable Circuits , 2009 .

[13]  Enrico Giunchiglia,et al.  Reasoning with Quantified Boolean Formulas , 2021, Handbook of Satisfiability.

[14]  Masahiro Fujita,et al.  On error tolerance and Engineering Change with Partially Programmable Circuits , 2012, 17th Asia and South Pacific Design Automation Conference.

[15]  Inês Lynce,et al.  The Seventh QBF Solvers Evaluation (QBFEVAL'10) , 2010, SAT.

[16]  Masahiro Fujita,et al.  Methods for automatic design error correction in sequential circuits , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[17]  R. Brayton,et al.  Improvements to Combinational Equivalence Checking , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.