IMPRoVED: Integrated Method to Predict PostRouting setup Violations in Early Design Stages

The detail routing process is by far the most time consuming during the physical design flow. Routing starts with an estimation of timing slacks and aims to meet the timing specifications at signoff. In this paper, we propose an improved method to predict the net delays using RandomForestRegressor and thereby predict critical paths early on at the placement stage. Quick timing prediction is also essential in making time-sensitive edits to stepping of the chip based on post-Si feedback. The proposed algorithm is based on five novel features, namely, targeted feature selection, introduction of a one-hot encoding scheme, an outlier identification method, post-route buffer-bloat prediction, and post-route cell sizing prediction. Experimental results on academic benchmarks and industry circuits, both on advanced 10nm process node show that the proposed algorithm has led to significant improvements in accurately predicting timing slacks when compared with state of the art. The proposed algorithm predicts slack within 0.598% of signoff results, whereas the state of art results are erroneous by an average of 53.33% for the same metric. Overall time savings of 44.1% is seen when compared to running the traditional flow, and savings of 90% is seen for obtaining the timing results.

[1]  Yao Wang,et al.  Accurate timing prediction at placement stage with look-ahead RC network , 2022, DAC.

[2]  Tsung-Wei Huang,et al.  GPU-Accelerated Static Timing Analysis , 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

[3]  William J. Dally,et al.  Accelerating Chip Design With Machine Learning , 2020, IEEE Micro.

[4]  Yiran Chen,et al.  Machine Learning-Based Pre-Routing Timing Prediction with Reduced Pessimism , 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

[5]  Andrew B. Kahng,et al.  "Unobserved Corner" Prediction: Reducing Timing Analysis Effort for Faster Design Convergence in Advanced-Node Design , 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[6]  Yusuke Matsui,et al.  Drive-Strength Selection for Synthesis of Leakage-Dominant Circuits , 2019, 20th International Symposium on Quality Electronic Design (ISQED).

[7]  Hao Chen,et al.  A Multithreaded Initial Detailed Routing Algorithm Considering Global Routing Guides , 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[8]  Andrew B. Kahng,et al.  Using Machine Learning to Predict Path-Based Slack from Graph-Based Timing Analysis , 2018, 2018 IEEE 36th International Conference on Computer Design (ICCD).

[9]  Balázs Kégl,et al.  Similarity encoding for learning with dirty categorical variables , 2018, Machine Learning.

[10]  Ismail Bustany,et al.  A Machine Learning Framework to Identify Detailed Routing Short Violations from a Placed Netlist , 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

[11]  Andrew B. Kahng,et al.  Machine Learning Applications in Physical Design: Recent Results and Directions , 2018, ISPD.

[12]  Andrew A. Kennings,et al.  Detailed routing violation prediction during placement using machine learning , 2017, 2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

[13]  Mateus Fogaça,et al.  Drive Strength Aware Cell Movement Techniques for Timing Driven Placement , 2016, ISPD.

[14]  Andrew B. Kahng,et al.  Learning-based prediction of embedded memory timing failures during initial floorplan design , 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

[15]  Andrew B. Kahng,et al.  SI for free: machine learning of interconnect coupling delay and transition effects , 2015, 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP).

[16]  Andrew B. Kahng,et al.  A deep learning methodology to proliferate golden signoff timing , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[17]  Andrew B. Kahng,et al.  Learning-based approximation of interconnect delay and slew in signoff timing tools , 2013, 2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP).

[18]  Kenneth M. Butler,et al.  Adaptive multidimensional outlier analysis for analog and mixed signal circuits , 2011, 2011 IEEE International Test Conference.

[19]  Jarrod A. Roy,et al.  What makes a design difficult to route , 2010, ISPD '10.

[20]  Davide Pandini,et al.  Statistical static timing analysis: A survey , 2009, Integr..

[21]  Rakesh Chadha,et al.  Static Timing Analysis for Nanometer Designs: A Practical Approach , 2009 .

[22]  David Blaauw,et al.  Circuit optimization using statistical static timing analysis , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[23]  Yehea I. Ismail,et al.  Statistical static timing analysis: how simple can we get? , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[24]  C. Alpert,et al.  Accurate estimation of global buffer delay within a floorplan , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[25]  Carl Sechen,et al.  Efficient timing closure without timing driven placement and routing , 2004, Proceedings. 41st Design Automation Conference, 2004..

[26]  Hongliang Chang,et al.  Statistical timing analysis considering spatial correlations using a single PERT-like traversal , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[27]  Chandramouli V. Kashyap,et al.  Block-based static timing analysis with uncertainty , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[28]  L. Breiman.  Random Forests , 2001, Encyclopedia of Machine Learning and Data Mining.

[29]  A. Gattiker,et al.  Timing yield estimation from static timing analysis , 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

[30]  A. Kahng,et al.  The OpenROAD Project: Unleashing Hardware Innovation , 2021 .

[31]  Bing Li,et al.  Statistical Static Timing Analysis , 2012 .

[32]  Shantanu Dutt,et al.  A Network-Flow Based Cell Sizing Algorithm , 2008 .

[33]  Martin D. F. Wong,et al.  Channel ordering for VLSI layout with rectilinear modules , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[34]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .