Segmented channel routability via satisfiability

Segmented channel routing is fundamental to the routing of row-based FPGAs. In this paper, we study segmented channel routability via satisfiability. Our method encodes the horizontal and vertical constraints of the routing problem as Boolean conditions. The routability constraint is satisfiable if and only if the net connections in the segmented channel are routable. Empirical results show that the method is time-efficient and applicable to large problem instances.

[1]  Kaushik Roy A bounded search algorithm for segmented channel routing for FPGA's and associated channel architecture issues , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Igor L. Markov,et al.  Solving difficult SAT instances in the presence of symmetry , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[3]  Matthew W. Moskewicz,et al.  Cha : Engineering an e cient SAT solver , 2001, DAC 2001.

[4]  Sharad Malik,et al.  Efficient conflict driven learning in a Boolean satisfiability solver , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[5]  Martin D. F. Wong,et al.  On channel segmentation design for row-based FPGAs , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[6]  Yao-Wen Chang,et al.  Algorithms for an FPGA switch module routing problem with application to global routing , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Rob A. Rutenbar,et al.  Satisfiability-based detailed FPGA routing , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[8]  Andrew A. Kennings,et al.  Board-level multiterminal net assignment for the partial cross-bar architecture , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Jonathan Rose,et al.  A detailed router for field-programmable gate arrays , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[10]  Vwani P. Roychowdhury,et al.  Segmented channel routing , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Malgorzata Marek-Sadowska,et al.  Graph based analysis of FPGA routing , 1993, EURO-DAC.

[12]  Massoud Pedram,et al.  Design and analysis of segmented routing channels for row-based FPGA's , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Cheng-Hsing Yang,et al.  Efficient routability check algorithms for segmented channel routing , 2000, TODE.

[14]  Jonathan Rose,et al.  A detailed router for field-programmable gate arrays , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Srinivas Devadas,et al.  Optimal layout via Boolean satisfiability , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[16]  Rob A. Rutenbar,et al.  A comparative study of two Boolean formulations of FPGA detailed routing constraints , 2001, IEEE Transactions on Computers.

[17]  Steven Trimberger Effects of FPGA Architecture on FPGA Routing , 1995, 32nd Design Automation Conference.

[18]  Sharad Malik,et al.  Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[19]  Ilkka Niemelä,et al.  Towards an Efficient Tableau Method for Boolean Circuit Satisfiability Checking , 2000, Computational Logic.

[20]  Rob A. Rutenbar,et al.  FPGA routing and routability estimation via Boolean satisfiability , 1997, FPGA '97.