Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode

This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-/spl kappa/ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of I/sub on//I/sub off//spl sim/10/sup 7/-10/sup 8/ and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi/sub 2-x/ S/D , I/sub on//I/sub off/ can reach /spl sim/10/sup 5/ at V/sub ds/ of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-/spl kappa/ dielectric and metal-gate materials to be used in the future generation CMOS technology.

[1]  M. P. Lepselter,et al.  SB-IGFET: An insulated-gate field-effect transistor using Schottky barrier contacts for source and drain , 1968 .

[2]  J. Knoch,et al.  Impact of the channel thickness on the performance of Schottky barrier metal–oxide–semiconductor field-effect transistors , 2002 .

[3]  High-performance p-channel Schottky-barrier SOI FinFET featuring self-aligned PtSi source/drain and electrical junctions , 2003, IEEE Electron Device Letters.

[4]  박경완,et al.  Characteristics of Erbium silicided n-type Schottky barrier tunnel transistors , 2003 .

[5]  C. R. Helms,et al.  Experimental investigation of a PtSi source and drain field emission transistor , 1995 .

[6]  J.C. Lee,et al.  Improved thermal stability and device performance of ultra-thin (EOT<10 /spl Aring/) gate dielectric MOSFETs by using hafnium oxynitride (HfO/sub x/N/sub y/) , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

[7]  J. Nogami,et al.  A scanning tunneling microscopy study of dysprosium silicide nanowire growth on Si(001) , 2003 .

[8]  Mark A. Reed,et al.  Suppression of leakage current in Schottky barrier metal–oxide–semiconductor field-effect transistors , 2002 .

[9]  C. Hu,et al.  Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[10]  D. Kwong,et al.  Robust high-quality HfN-HfO/sub 2/ gate stack for advanced MOS device applications , 2004, IEEE Electron Device Letters.

[11]  Karen Maex,et al.  Properties of metal silicides , 1995 .

[12]  Tung,et al.  Electron transport at metal-semiconductor interfaces: General theory. , 1992, Physical review. B, Condensed matter.

[13]  D.S.H. Chan,et al.  Thermally robust high quality HfN/HfO/sub 2/ gate stack for advanced CMOS devices , 2003, IEEE International Electron Devices Meeting 2003.